Dr. Somesh Kumar

Dr. Somesh Kumar

Designation: Assistant Professor

Department: Electrical / Electronics

Honour: Ph.D. in Electrical Engineering (IIT Ropar, Punjab)

Area of Interest: Design and Fabrication of high-speed chip-chip and 3D interconnects, 3D Integration and TSVs, Graphene based nanoelectronic devices and interconnects, 3D IC design, Interconnect architecture for Network-on-chips, Flexible Devices.

Office Phone : +91-751-2449811

Address: F Block -205, ABV-IIITM, Morena Link Road, Gwalior-474015 (M.P.)

Email: somesh@iiitm.ac.in

Website: https://sites.google.com/iiitm.ac.in/skumar

Biography

Dr. Somesh Kumar joined the ABV-IIITM in 2019, where he is currently an Assistant Professor. Before joining IIITM Gwalior, Dr. Kumar was an Assistant Professor at the Indian Institute of Information Technology Nagpur (IIITN), Nagpur. All along his tenure at IIIT Nagpur, he has initiated activities in the area of VLSI Design and Nanoelectronics. He has established the HDL Lab, Digital and Analog Electronics Lab for undergraduate studies.  

Dr. Kumar received the B. Tech. degree in Electronics and Telecommunication Engineering from Kurukshetra University (Ch. Devilal Memorial Government Engineering College) in 2009, the M. Tech degree in VLSI Design & CAD from Thapar University in 2012 under the supervision of Prof. Ravi Kumar. He did Ph. D. degree in Electrical Engineering from Indian Institute of Technology Ropar (IIT Ropar) in 2018. His Ph. D. supervisor was Prof. Rohit Y. Sharma - with whom he learned the rudiments of high-speed interconnect design and 3D IC Design. During his doctoral studies, he worked on modeling, fabrication and performance benchmarking of on-chip and chip-to-chip interconnects considering surface roughness. His current research interests include design and fabrication of high-speed chip-chip, on-chip and 3D interconnects. Recently, he also started working on graphene based and flexible devices.

He is a referee for several journals including IEEE Transactions on Electromagnetic Compatibility, IEEE Transactions on Emerging Topics in Computing, IEEE Transactions on Components, Packaging and Manufacturing Techniques, IET Digital & computer techniques and Journal of Supercomputing. He is a Senior Member of the IEEE and convener of IEEE student branch at ABV-IIITM, Gwalior.

Teaching Interests:

  • Electronic Devices and Circuits
  • Digital Electronic Circuits
  • Hardware Description Languages (HDL)
  • Microelectronic Circuit Design
  • VLSI Design and Application
  • IC Fabrication
  • CAD For VLSI
  • Design and Modelling of Nano-scale devices & Interconnects
  • 3D IC Design

Research Interests: Design and Fabrication of high-speed chip-chip and 3D interconnects, 3D Integration and TSVs, Graphene based nanoelectronic devices and interconnects, 3D IC design, Interconnect architecture for Network-on-chips, Flexible Devices

Publications:

  1. Kumar, and R. Sharma, “Investigating the Role of Interconnect Surface Roughness towards the Design of Power-Aware Network on Chip”, IET Computers and Digital Techniques, vol. 13, no. 1, pp. 49-56, 2019.
  2. Kumar, and R. Sharma, “Chip-to-Chip Copper Interconnects with Rough Surfaces: Analytical models for Parameter Extraction and Performance Evaluation”, IEEE Tran. on Components, Packaging and Manufacturing Technology, vol. 8, no. 2, pp. 286-299, 2018.
  3. Kumar, and R. Sharma, “Analytical Model for Resistivity and Mean Free Path in On-Chip Interconnect with Rough Surfaces”, IEEE Tran. on Emerging Topics in Computing, vol. 6, no. 2, pp. 233-243, 2018.
  4. Kumar, and R. Sharma, “Analytical Modeling and Performance Benchmarking of On-Chip Interconnects with Rough Surfaces”, IEEE Tran. on Multi-scale Computing System, vol. 4, no. 3, pp. 272-284, 2018.
  5. Kumar and Monika, “Study of Effect of Variations in slot dimensions on Fractal Patch antenna Performance”, International Journal of Computers & Technology, vol. 5, no. 1, pp. 41-48, 2013.
  6. Kumar and R. Kumar, “A 1.8V and 2GHz Inductively Degenerated CMOS Low Noise Amplifier”, International Journal of Electronics Communication and Computer Technology, vol. 2, no. 4, pp. 150-154, 2012.
  7. Kumar and Kuldeepak, “A 0.18µm and 2GHz CMOS Differential Low Noise Amplifier”, International Journal of Electronics Communication and Computer Technology, vol. 2, no. 4, pp. 155-158, 2012.
  8. Kumar et al., “Crosstalk Analysis for Rough Copper Interconnects considering Ternary Logic” in proc. IEEE EDAPS, Chandigarh, India, 2018.
  9. Kumar et al., “A Shortest Path Algorithm for 3D Integrated Circuit TSV Assignment” in proc. IEEE EDAPS, Chandigarh, India, 2018.
  10. Kumar et al., “Investigating the Role of Surface Roughness on the Performance of Through Silicon Vias”, in proc. IEEE Electronics Packaging Technology Conference (EPTC), Singapore, 2017, pp. 1-4.
  11. Kumar, and R. Sharma, “Performance Modeling and Broadband Characterization of Chip-to-Chip Interconnects with Rough Surfaces”, in proc. IEEE Electronics Packaging Technology Conference (EPTC), Singapore, 2016, pp. 629-632.
  12. Kumar, and R. Sharma, “Design Space Exploration of Nanoscale Interconnects with Rough Surfaces”, in proc. IEEE Electrical Design of Advanced Packaging and System Symposium (EDAPS), Seoul, South Korea, 2015, pp. 125-128.
  13. Kumar et al., “A High-k, Metal Gate Vertical-Slit FET for Ultra-Low Power and High-Speed Applications”, in proc. IEEE International India conference (INDICON), New Delhi, India, 2015, pp. 1-5.
  14. Kumar, and Sudha, “ Design of Low Power, High Gain LNA for WCDMA range and Parameters Extraction using Artificial Neural Network (ANN), in proc. IEEE Power, Communication and Information Technology (PCITC), Bhubaneshwar, India, 2015, pp. 436-441.
  15. Kumar et al., “Analytical Model for Design of Complementary Inverter using Floating Gate Graphene Field Effect Transistors”, in proc. ISVLSI, Tampa, Florida, USA, 2014, pp. 148-153.
  16. Kumar et al., “Design Space Exploration of Through Silicon Vias for High-Speed, Low Loss Vertical Links”, in proc. IEEE Electrical Design of Advanced Packaging and System Symposium (EDAPS), Bangalore, India, 2014, pp. 9-12.
  17. Kumar et al., “Low Power CMOS Current Reuse Low Noise Amplifier at 2.4 GHz Frequency”, in proc. IEEE International conference on research and development prospects on Engineering and technology, Tamilnadu, India, 2013, pp. 68-70.
  18. Kumar, “Fast Adders Synthesis and Simulation using VHDL”, in proc. National Conference on Latest Advancement in Science, Engineering and Research 2011 (LASER’11), Bhatinda, India, 2011, pp. 140-143.

Conference/Workshop/Symposium organized:

  1. Title: “IEEE Advanced Semiconductor Packaging Workshop”
    Role: Organizing Member
    Funding Agency: IEEE Delhi Chapter and IEEE Electronics Packaging Society
    Duration: 07 Nov. 2015
    Place: Indian Institute of Technology Ropar, Rupnagar

Invited Talks:

  1. Invited Talk at Faculty development Program titled "Advanced CMOS VLSI" at Electronics & Communication Engineering, NIT Warangal, India held in Dec. 2018.

Achievements:

  • Member, Editorial Board of International Journal for scientific Research and Development.
  • Member, Institute of Electrical and Electronic Engineers (IEEE).
  • Member, Indian Society for Technical Education (ISTE).
  • Referee, IEEE Transactions on Electromagnetic Compatibility, IEEE Transactions on Emerging Topics in Computing, IEEE Transactions on Components, Packaging and Manufacturing Techniques.
  • Reviewer, IEEE Transactions on Emerging Topics in Computing.
  • Best paper Award in IEEE Electronics Packaging Technology Conference (EPTC), Singapore, 2017.
  • Recipient of the CEFIPRA-ESONN (France) Fellowship, 2015.
  • Recipient of CSIR International travel grant to attend IEEE EDAPS held at South Korea, 2016.

Connect with us

ABV-Indian Institute of Information Technology and Management Gwalior, Morena Link Road, Gwalior, Madhya Pradesh, India,474015

  • dummy info@iiitm.ac.in

Newsletter

Enter your email and we'll send you more information

Search