Fully Funded by Ministry of Education, Govt. of India

शिक्षा मंत्रालय, भारत सरकार द्वारा वित्त पोषित

Dr. Saumya Bhadauria

Dr. Saumya Bhadauria

Designation: Assistant Professor

Department: Computer Science

Honour: Ph.D. (IIT-Indore)

Area of Interest: Computer Organization and Architecture, Information security, Network security, Optimization techniques

Office Phone : +91-751-2449820

Address: C Block -108, ABV-IIITM, Morena Link Road, Gwalior-474015 (M.P.)

Email: saumya@iiitm.ac.in



  1. PhD (IIT, Indore) in April 2016
  2. University Grant Commission (UGC) NET awardee in Computer Science and Applications discipline in JUNE 2012.

International Journals   :

  1. Anirban Sengupta, Saumya Bhadauria and Saraju P. Mohanty, “Low Cost Security Aware High Level Synthesis Methodology”, IET Computers & Digital Techniques, Volume 11, Issue 2, March 2017.
  2. Anirban Sengupta, Saumya Bhadauria and Saraju P. Mohanty, “TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling with Optimal Loop Unrolling Factor during High Level Synthesis”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 4, pp. 655-668, April 2017.
  3. Anirban Sengupta, Saumya Bhadauria, “IP core Protection of CDFGs using Robust Watermarking during Behavioral Synthesis Based on User Resource Constraint and Loop Unrolling Factor”, IET Electronics Letters, Vol. 52 No. 6 pp. 439-441, March 2016.
  4. Anirban Sengupta, Saumya Bhadauria, “Exploring Low Cost Optimal Watermark for Reusable IP Cores during High Level Synthesis”, IEEE Access Journal, vol. 4, no., pp. 2198-2215, 2016.
  5. Anirban Sengupta, Saumya Bhadauria, “Optimized Hardware Design for Trojan Security at Behavioural Level for Loop Based Applications”, Elsevier Journal on VLSI Integration, Invited Paper, Jan 2016.
  6. Saumya Bhadauria, Anirban Sengupta “Adaptive bacterial foraging optimization driven Design Space Exploration: Exploring area-performance tradeoff during HLS”, Elsevier Journal on Applied Mathematics and Computations, Volume 269, pp. 265–278, Oct 2015.
  7. Anirban Sengupta, Saumya Bhadauria, “Bacterial Foraging Driven Exploration of Multi Cycle Fault Tolerant Datapath based on Power-Performance Tradeoff in High Level Synthesis”, Elsevier Journal on Expert Systems With Applications, Volume 42, pp. 4719 - 4732, Jan 2015.
  8. Anirban Sengupta, Saumya Bhadauria, “Automated Design Space Exploration of Multi-Cycle Transient Fault Detectable Datapath based on Multi-Objective User Constraints for Application Specific Computing”, Elsevier Journal on Advances in Engineering Software, Volume 82, pp. 14- 24, April 2015.
  9. Saumya Bhadauria, Anirban Sengupta, “Multi-Cycle Single Event Transient Fault Security Aware MO-DSE for Single loop CDFGs in HLS”, IEEE VLSI Circuits & Systems Letters, Volume 1, Issue 2, Oct 2015.
  10. Anirban Sengupta, Saumya Bhadauria, “Exploration of Multi-Objective Tradeoff During High Level Synthesis Using Bacterial Chemotaxis and Dispersal”, Elsevier Journal on Procedia Computer Science, Volume 35, Issue C, pp. 63 -72, Sep 2014.

 Conferences :

  1. Anirban Sengupta, Saumya Bhadauria, Saraju Mohanty "Embedding Low Cost Optimal Watermark During High Level Synthesis for Reusable IP Core Protection", Proc. of 48th IEEE Int'l Symposium on Circuits & Systems (ISCAS), Montreal, May 2016.
  2. Anirban Sengupta, Saumya Bhadauria, “User Power-Delay Budget Driven PSO Based Design Space Exploration of Optimal k-cycle Transient Fault Secured Datapath during High Level Synthesis”, Proceedings of 16th IEEE International Symposium on Quality Electronic Design (ISQED), California, USA, March 2015, pp. 289 - 292 (DOUBLE BLIND REVIEW).
  3. Anirban Sengupta, Saumya Bhadauria, “Automated Design Space Exploration of Transient Fault Detectable Datapath Based on User Specified Power and Delay Constraints”, Proceedings of 33rd VLSI - Design Automation & Test (VLSI - DAT),Taiwan, April 2015, pp. 1-4 (DOUBLE BLIND REVIEW).
  4. Anirban SenguptaSaumya Bhadauria “Untrusted Third Party Digital IP cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis”,  Proceedings of 25th IEEE/ACM Great Lake Symposium on VLSI (GLSVLSI), Pennsylvania, May 2015, pp. 167 - 172 (DOUBLE BLIND REVIEW).
  5. Anirban Sengupta, Saumya Bhadauria, “Secure Information Processing during System level: Exploration of an Optimized Trojan Secured Datapath for CDFGs during HLS based on User Constraints”, Proceedings of 1st IEEE iNIS 2015 Dec 2015, pp. 1 – 6.
  6. Anirban Sengupta, Saumya Bhadauria, “Automated Exploration of Datapath in High Level Synthesis using Temperature Dependent Bacterial Foraging Optimization Algorithm”, Proceedings of 27th IEEE Canadian Conference on Electrical and Computer EngineeringToronto, May 2014, pp. 68 -73.
  7. Anirban Sengupta, Saumya Bhadauria, “Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay Budget”, Proceedings of 13th IEEE International Conference on Information Technology, Dec 2014, pp. 345 - 350 (DOUBLE BLIND REVIEW).­­

 Achievements  :

  • Travel grant by Department of Science and Technology, India for presenting research work in ISQED 2015, California, USA.
  • Travel grant by Council of Science and Industrial Research, India for presenting research work in VLSI - DAT,April 2015, Taiwan.
  • Travel grant by Asia and South Pacific Design Automation Conference, 2016 for presenting research work in January 2016.
  • MHRD Fellowship, Ph.D. (IIT Indore): 2013-2016
  • GATE 2011 in Computer Science and Engineering 2011.

ORCID ID                                           : orcid.org/0000-0002-6502-2695

Scopus Author ID                                : 56400656200

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