Dr. Gaurav Kaushal

Dr. Gaurav Kaushal

Designation: Assistant Professor

Honour: PhD (IIT, Roorkee)

Area of Interest: Microelectronics, Device Modelling, Low Power Circuit

Office Phone : +91-751-2449633

Address: D Block -115, ABV-IIITM, Morena Link Road, Gwalior-474015 (M.P.)

Email: kaushalg@iiitm.ac.in

Biography

Dr. Gaurav Kaushal received the Ph.D. degree from Indian Institute of Technology Roorkee, and M. Tech. degree from M.A.N.I.T. Bhopal in 2013 and, 2008 respectively. He has authored and coauthored over 17 papers in journals and conference proceedings in various areas of CMOS devices and circuits. He has post-doctoral experience in VLSI System Laboratory, Yonsei University, South Korea, from May’2014 to August’2015. He is a member IEEE’ Electronic Devices. He is a reviewer of IET Circuits, IEEE TDMR, and IEEE Transactions on Electronics Devices. He served in National Institute of Technology Patna, India from August’ 2015 – May’2017. Presently he is with ABV-Indian Institute of Information Technology & Management (IIITM), Gwalior, India. His research interests include novel CMOS devices such as nanowire/FinFET, circuit co-design and device modelling.

ORCID ID : orcid.org/0000-0002-7278-1104

Scopus Author ID : 24178210100

  1. Gaurav Kaushal, H. Jeong, Satish Maheshwaram, S. K. Manhas, S. Dasgupta, S. O. Jung, ”Low Power SRAM design for 14nm GAA Si-Nanowire Technology” in Elsevier Microelectronics Engineering, 46, no. 12, pp. 1239-1247, Dec. 2015..
  2. Gaurav Kaushal, S. K. Manhas, S. Maheshwaram, S. Dasgupta, B. Anand, and N. Singh, “Novel
    Design Methodology using LEXT sizing in Nanowire CMOS Logic” in IEEE Transactions on
    Nanotechnology
    , vol. 13, no. 4, pp. 650-658, Jul. 2014.
  3. Ravi Shankar, Gaurav Kaushal, , S. Maheshwaram, Dasgupta, and S. K. Manhas, “A Degradation Model of Double Gate and Gate-All-Around MOSFETs with Interface Trapped Charges Including Effects of Channel Mobile Charge Carriers” in IEEE Transactions on Device and Materials Reliability, vol. 14, no. 2, pp. 689-697, June, 2014.
  4. Gaurav Kaushal, K. Manhas, S. Maheshwaram, and S. DasguptaImpact of Series Resistance on Si Nanowire MOSFET Performance” Springer Journal of Computational Electronics, no. 13, pp. 449-458, March 2013.
  5. Maheshwaram, S. K. Manhas, Gaurav Kaushal, B. Anand, and N. Singh, “Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis” in IEEE Transactions on Electron Devices , vol. 60, no. 9, pp. 2943-2950, Sept 2013.
  6. Gaurav Kaushal, K. Manhas, S. Maheshwaram, S. Dasgupta, B. Anand, and N. Singh, “Tuning Source/Drain Extension Profile for Current Matching in Nanowire CMOS Logic” in IEEE Transactions on Nanotechnology, vol. 11, no. 5, pp. 1033-1039, Sep. 2012.
  7. Gaurav Kaushal, S. S. rathod, S. Maheshwaram, S. K. Manhas, A. K. Saxena, and S. Dasgupta, “Radiation Effects in Si-NW GAA FET and CMOS Inverter: A TCAD Simulation Study” in IEEE Transactions on Electron Devices, vol. 59, no. 5, pp. 1563-1566, May 2012.
  8. Maheshwaram, S. K. Manhas, Gaurav Kaushal, B. Anand, and N. Singh, “Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform” in IEEE Electron Device Letter, vol. 33, no. 7, pp. 934-936, Jul. 2012.
  9. Maheshwaram, S. K. Manhas, Gaurav Kaushal, B. Anand, and N. Singh, “Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS” in IEEE Electron Device Letter, vol. 32, no. 8, pp. 1011-1013, Aug. 2011.

 Conferences  :

  1. Kaushal, H. Jeong, S. O. Jung, Subramanyam, S. N. Rao, Vidya, R. Ramya, S. Shaik and R. Vaddi, "Design and Performance Benchmarking of Steep-Slope Tunnel Transistors for Low Voltage Digital and Analog Circuits Enabling Self-Powered SOCs", Proc. IEEE International SoC Design Conference (ISOCC), South Korea, pp. 32-33, 2014.
  2. S Maheshwaram, S. K. Manhas, Kaushal, B. Anand, “Vertical nanowire MOSFET parasitic resistance modeling”, Proc. IEEE Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, pp. 1-2, 2013.
  3. Kaushal, S. Maheshwaram, S. Dasgupta and S. K. Manhas, "Drive Matching Issues in Multi Gate CMOS", in International Conference on Signal Processing and Communication (ICSC), pp. 349-354, 2013.
  4. Gaurav Kaushal, S. Rathod, Satish Maheshwaram, S. K. Manhas, A. K. Saxena and S. Dasgupta, “Single Event Upset in Si Nanowire GAA FET Based CMOS Inverter,” in International Workshop on Physics of Semiconductor Devices (IWPSD) Dec. 2011.
  5. Gaurav Kaushal, Satish Maheshwaram, S. Dasgupta and S.K. Manhas, “Analysis of Series Resistance in si-nanowire FET,” in VLSI Design and Test Symposium (VDAT) 2011.
  6. Gaurav Kaushal, Satish Maheshwaram, S. Dasgupta and S.K. Manhas, “Si-Nanowire FET Device and Circuit Performance with progressive technology scaling, Conf. on Communication, Computers, and devices,” IIT Kharagpur, India, pp. 1-6, Dec. 2010.
  7. Satish Maheshwaram, Gaurav Kaushal, S. K. Manhas, "A High Performance Vertical Si Nanowire CMOS for Ultra High Density Circuits," Proc. IEEE Asia Pacific Conf. on Circuit and System (APCCAS), pp. 1219-1222, Dec. 2010, Kuala Lumpur, Malaysia.

हमसे जुडे

एबीवी-भारतीय सूचना प्रौद्योगिकी और प्रबंधन संस्थान ग्वालियर, मोरेना लिंक रोड, ग्वालियर, मध्य प्रदेश, भारत, 474015

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